MOV -- Move Data

Operation

 
 
 DEST := SRC;
 

Description

If the destination operand is a segment register (DS, ES, SS, etc.), then data from a descriptor is also loaded into the register. The data for the register is obtained from the descriptor table entry for the selector given. A null selector (values 0000-0003) can be loaded into DS and ES registers without causing an exception; however, use of DS or ES causes a #GP(0), and no memory reference occurs.

A MOV into SS inhibits all interrupts until after the execution of the next instruction (which is presumably a MOV into eSP).

Loading a segment register under 80386 Protected Mode results in special checks and actions, as described in the following listing:

 
 
 IF SS is loaded;
 THEN
    IF selector is null THEN #GP(0);
 FI;
    Selector index must be within its descriptor table limits else
       #GP(selector);
    Selector's RPL must equal CPL else #GP(selector);
 AR byte must indicate a writable data segment else #GP(selector);
    DPL in the AR byte must equal CPL else #GP(selector);
    Segment must be marked present else #SS(selector);
    Load SS with selector;
    Load SS with descriptor.
 FI;
 IF DS, ES, FS or GS is loaded with non-null selector;
 THEN
    Selector index must be within its descriptor table limits
       else #GP(selector);
    AR byte must indicate data or readable code segment else
       #GP(selector);
    IF data or nonconforming code segment
    THEN both the RPL and the CPL must be less than or equal to DPL in
       AR byte;
    ELSE #GP(selector);
    FI;
    Segment must be marked present else #NP(selector);
    Load segment register with selector;
    Load segment register with descriptor;
 FI;
 IF DS, ES, FS or GS is loaded with a null selector;
 THEN
    Load segment register with selector;
    Clear descriptor valid bit;
 FI;
 

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

MOV -- Move to/from Special Registers

Operation

 
 
 DEST := SRC;
 

Description

• Control registers CR0, CR2, and CR3
• Debug Registers DR0, DR1, DR2, DR3, DR6, and DR7
• Test Registers TR6 and TR7

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

Notes

The reg field within the ModRM byte specifies which of the special registers in each category is involved. The two bits in the field are always 11. The r/m field specifies the general register involved.

MOVS/MOVSB/MOVSW/MOVSD -- Move Data from String to String

Operation

 
 
 IF (instruction = MOVSD) OR (instruction has doubleword operands)
 THEN OperandSize := 32;
 ELSE OperandSize := 16;
 IF AddressSize = 16
 THEN use SI for source-index and DI for destination-index;
 ELSE (* AddressSize = 32 *)
    use ESI for source-index and EDI for destination-index;
 FI;
 IF byte type of instruction
 THEN
    [destination-index] := [source-index]; (* byte assignment *)
    IF DF = 0 THEN IncDec := 1 ELSE IncDec := -1; FI;
 ELSE
    IF OperandSize = 16
    THEN
       [destination-index] := [source-index]; (* word assignment *)
       IF DF = 0 THEN IncDec := 2 ELSE IncDec := -2; FI;
    ELSE (* OperandSize = 32 *)
       [destination-index] := [source-index]; (* doubleword assignment *)
       IF DF = 0 THEN IncDec := 4 ELSE IncDec := -4; FI;
    FI;
 FI;
 source-index := source-index + IncDec;
 destination-index := destination-index + IncDec;
 

Description

The addresses of the source and destination are determined solely by the contents of (E)SI and (E)DI. Load the correct index values into (E)SI and (E)DI before executing the MOVS instruction. MOVSB, MOVSW, and MOVSD are synonyms for the byte, word, and doubleword MOVS instructions.

After the data is moved, both (E)SI and (E)DI are advanced automatically. If the direction flag is 0 (CLD was executed), the registers are incremented; if the direction flag is 1 (STD was executed), the registers are decremented. The registers are incremented or decremented by 1 if a byte was moved, 2 if a word was moved, or 4 if a doubleword was moved.

MOVS can be preceded by the REP prefix for block movement of CX bytes or words. Refer to the REP instruction for details of this operation.

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

MOVSX -- Move with Sign-Extend

Operation

 
 
 DEST := SignExtend(SRC);
 

Description

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

MOVZX -- Move with Zero-Extend

Operation

 
 
 DEST := ZeroExtend(SRC);
 

Description

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

MUL -- Unsigned Multiplication of AL or AX

 
 
     Actual clock = if  <> 0 then max(ceiling(log{2}(m)), 3) + 6 clocks;
 
     Actual clock = if  = 0 then 9 clocks
 

Operation

 
 
 IF byte-size operation
 THEN AX := AL * r/m8
 ELSE (* word or doubleword operation *)
    IF OperandSize = 16
    THEN DX:AX := AX * r/m16
    ELSE (* OperandSize = 32 *)
       EDX:EAX := EAX * r/m32
    FI;
 FI;
 

Description

• A byte operand is multiplied by AL; the result is left in AX. The carry and overflow flags are set to 0 if AH is 0; otherwise, they are set to 1.
• A word operand is multiplied by AX; the result is left in DX:AX. DX contains the high-order 16 bits of the product. The carry and overflow flags are set to 0 if DX is 0; otherwise, they are set to 1.
• A doubleword operand is multiplied by EAX and the result is left in EDX:EAX. EDX contains the high-order 32 bits of the product. The carry and overflow flags are set to 0 if EDX is 0; otherwise, they are set to 1.

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

NEG -- Two's Complement Negation

Operation

 
 
 IF r/m = 0 THEN CF := 0 ELSE CF := 1; FI;
 r/m := - r/m;
 

Description

The carry flag is set to 1, unless the operand is zero, in which case the carry flag is cleared to 0.

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

NOP -- No Operation

Description

NOP is an alias mnemonic for the XCHG (E)AX, (E)AX instruction.

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

NOT -- One's Complement Negation

Operation

 
 
 r/m := NOT r/m;
 

Description

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

OR -- Logical Inclusive OR

Operation

 
 
 DEST := DEST OR SRC;
 CF := 0;
 OF := 0
 

Description

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

OUT -- Output to Port

 
 
    *If CPL <= IOPL
   **If CPL > IOPL or if in virtual 8086 mode
 

Operation

 
 
 IF (PE = 1) AND ((VM = 1) OR (CPL > IOPL))
 THEN (* Virtual 8086 mode, or protected mode with CPL > IOPL *)
    IF NOT I-O-Permission (DEST, width(DEST))
    THEN #GP(0);
    FI;
 FI;
 [DEST] := SRC; (* I/O address space used *)
 

Description

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

OUTS/OUTSB/OUTSW/OUTSD -- Output String to Port

 
 
    *If CPL <= IOPL
   **If CPL > IOPL or if in virtual 8086 mode
 

Operation

 
 
 IF AddressSize = 16
 THEN use SI for source-index;
 ELSE (* AddressSize = 32 *)
    use ESI for source-index;
 FI;
 
 IF (PE = 1) AND ((VM = 1) OR (CPL > IOPL))
 THEN (* Virtual 8086 mode, or protected mode with CPL > IOPL *)
    IF NOT I-O-Permission (DEST, width(DEST))
    THEN #GP(0);
    FI;
 FI;
 IF byte type of instruction
 THEN
    [DX] := [source-index]; (* Write byte at DX I/O address *)
    IF DF = 0 THEN IncDec := 1 ELSE IncDec := -1; FI;
 FI;
 IF OperandSize = 16
 THEN
    [DX] := [source-index]; (* Write word at DX I/O address *)
    IF DF = 0 THEN IncDec := 2 ELSE IncDec := -2; FI;
 FI;
 IF OperandSize = 32
 THEN
    [DX] := [source-index]; (* Write dword at DX I/O address *)
    IF DF = 0 THEN IncDec := 4 ELSE IncDec := -4; FI;
    FI;
 FI;
 source-index := source-index + IncDec;
 

Description

OUTS does not allow specification of the port number as an immediate value. The port must be addressed through the DX register value. Load the correct value into DX before executing the OUTS instruction.

The address of the source data is determined by the contents of source-index register. Load the correct index value into SI or ESI before executing the OUTS instruction.

After the transfer, source-index register is advanced automatically. If the direction flag is 0 (CLD was executed), the source-index register is incremented; if the direction flag is 1 (STD was executed), it is decremented. The amount of the increment or decrement is 1 if a byte is output, 2 if a word is output, or 4 if a doubleword is output.

OUTSB, OUTSW, and OUTSD are synonyms for the byte, word, and doubleword OUTS instructions. OUTS can be preceded by the REP prefix for block output of CX bytes or words. Refer to the REP instruction for details on this operation.

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

POP -- Pop a Word from the Stack

Operation

 
 
 IF StackAddrSize = 16
 THEN
    IF OperandSize = 16
    THEN
       DEST := (SS:SP); (* copy a word *)
       SP := SP + 2;
    ELSE (* OperandSize = 32 *)
       DEST := (SS:SP); (* copy a dword *)
       SP := SP + 4;
    FI;
 ELSE (* StackAddrSize = 32 * )
    IF OperandSize = 16
    THEN
       DEST := (SS:ESP); (* copy a word *)
       ESP := ESP + 2;
    ELSE (* OperandSize = 32 *)
       DEST := (SS:ESP); (* copy a dword *)
       ESP := ESP + 4;
    FI;
 FI;
 

Description

POP CS is not an 80386 instruction. Popping from the stack into the CS register is accomplished with a RET instruction.

If the destination operand is a segment register (DS, ES, FS, GS, or SS), the value popped must be a selector. In protected mode, loading the selector initiates automatic loading of the descriptor information associated with that selector into the hidden part of the segment register; loading also initiates validation of both the selector and the descriptor information.

A null value (0000-0003) may be popped into the DS, ES, FS, or GS register without causing a protection exception. An attempt to reference a segment whose corresponding segment register is loaded with a null value causes a #GP(0) exception. No memory reference occurs. The saved value of the segment register is null.

A POP SS instruction inhibits all interrupts, including NMI, until after execution of the next instruction. This allows sequential execution of POP SS and POP eSP instructions without danger of having an invalid stack during an interrupt. However, use of the LSS instruction is the preferred method of loading the SS and eSP registers.

Loading a segment register while in protected mode results in special checks and actions, as described in the following listing:

 
 
 IF SS is loaded:
    IF selector is null THEN #GP(0);
    Selector index must be within its descriptor table limits ELSE
       #GP(selector);
    Selector's RPL must equal CPL ELSE #GP(selector);
    AR byte must indicate a writable data segment ELSE #GP(selector);
    DPL in the AR byte must equal CPL ELSE #GP(selector);
    Segment must be marked present ELSE #SS(selector);
    Load SS register with selector;
    Load SS register with descriptor;
 
 IF DS, ES, FS or GS is loaded with non-null selector:
    AR byte must indicate data or readable code segment ELSE
       #GP(selector);
    IF data or nonconforming code
    THEN both the RPL and the CPL must be less than or equal to DPL in
       AR byte
    ELSE #GP(selector);
    FI;
    Segment must be marked present ELSE #NP(selector);
    Load segment register with selector;
    Load segment register with descriptor;
 
 IF DS, ES, FS, or GS is loaded with a null selector:
    Load segment register with selector
    Clear valid bit in invisible portion of register
 

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

POPA/POPAD -- Pop all General Registers

Operation

 
 
 IF OperandSize = 16 (* instruction = POPA *)
 THEN
    DI := Pop();
    SI := Pop();
    BP := Pop();
    throwaway := Pop (); (* Skip SP *)
    BX := Pop();
    DX := Pop();
    CX := Pop();
    AX := Pop();
 ELSE (* OperandSize = 32, instruction = POPAD *)
    EDI := Pop();
    ESI := Pop();
    EBP := Pop();
    throwaway := Pop (); (* Skip ESP *)
    EBX := Pop();
    EDX := Pop();
    ECX := Pop();
    EAX := Pop();
 FI;
 

Description

POPAD pops the eight 32-bit general registers. The ESP value is discarded instead of loaded into ESP. POPAD reverses the previous PUSHAD, restoring the general registers to their values before PUSHAD was executed. The first register popped is EDI.

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

POPF/POPFD -- Pop Stack into FLAGS or EFLAGS Register

Operation

Description

Refer to Chapter 2 and Chapter 4 for information about the FLAGS and EFLAGS registers. Note that bits 16 and 17 of EFLAGS, called VM and RF, respectively, are not affected by POPF or POPFD.

The I/O privilege level is altered only when executing at privilege level 0. The interrupt flag is altered only when executing at a level at least as privileged as the I/O privilege level. (Real-address mode is equivalent to privilege level 0.) If a POPF instruction is executed with insufficient privilege, an exception does not occur, but the privileged bits do not change.

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

PUSH -- Push Operand onto the Stack

Operation

 
 
 IF StackAddrSize = 16
 THEN
    IF OperandSize = 16 THEN
       SP := SP - 2;
       (SS:SP) := (SOURCE); (* word assignment *)
    ELSE
       SP := SP - 4;
       (SS:SP) := (SOURCE); (* dword assignment *)
    FI;
 ELSE (* StackAddrSize = 32 *)
    IF OperandSize = 16
    THEN
       ESP := ESP - 2;
       (SS:ESP) := (SOURCE); (* word assignment *)
    ELSE
       ESP := ESP - 4;
       (SS:ESP) := (SOURCE); (* dword assignment *)
    FI;
 FI;
 

Description

The 80386 PUSH eSP instruction pushes the value of eSP as it existed before the instruction. This differs from the 8086, where PUSH SP pushes the new value (decremented by 2).

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

PUSHA/PUSHAD -- Push all General Registers

Operation

 
 
 IF OperandSize = 16 (* PUSHA instruction *)
 THEN
    Temp := (SP);
    Push(AX);
    Push(CX);
    Push(DX);
    Push(BX);
    Push(Temp);
    Push(BP);
    Push(SI);
    Push(DI);
 ELSE (* OperandSize = 32, PUSHAD instruction *)
    Temp := (ESP);
    Push(EAX);
    Push(ECX);
    Push(EDX);
    Push(EBX);
    Push(Temp);
    Push(EBP);
    Push(ESI);
    Push(EDI);
 FI;
 

Description

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

PUSHF/PUSHFD -- Push Flags Register onto the Stack

Operation

 
 
 IF OperandSize = 32
 THEN push(EFLAGS);
 ELSE push(FLAGS);
 FI;
 

Description

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

RCL/RCR/ROL/ROR -- Rotate

Operation

 
 
 (* ROL - Rotate Left *)
 temp := COUNT;
 WHILE (temp <> 0)
 DO
    tmpcf := high-order bit of (r/m);
    r/m := r/m * 2 + (tmpcf);
    temp := temp - 1;
 OD;
 IF COUNT = 1
 THEN
    IF high-order bit of r/m <> CF
    THEN OF := 1;
    ELSE OF := 0;
    FI;
 ELSE OF := undefined;
 FI;
 (* ROR - Rotate Right *)
 temp := COUNT;
 WHILE (temp <> 0 )
 DO
    tmpcf := low-order bit of (r/m);
    r/m := r/m / 2 + (tmpcf * 2^(width(r/m)));
    temp := temp - 1;
 DO;
 IF COUNT = 1
 THEN
    IF (high-order bit of r/m) <> (bit next to high-order bit of r/m)
    THEN OF := 1;
    ELSE OF := 0;
    FI;
 ELSE OF := undefined;
 FI;
 

Description

For the RCL and RCR instructions, the carry flag is part of the rotated quantity. RCL shifts the carry flag into the bottom bit and shifts the top bit into the carry flag; RCR shifts the carry flag into the top bit and shifts the bottom bit into the carry flag. For the ROL and ROR instructions, the original value of the carry flag is not a part of the result, but the carry flag receives a copy of the bit that was shifted from one end to the other.

The rotate is repeated the number of times indicated by the second operand, which is either an immediate number or the contents of the CL register. To reduce the maximum instruction execution time, the 80386 does not allow rotation counts greater than 31. If a rotation count greater than 31 is attempted, only the bottom five bits of the rotation are used. The 8086 does not mask rotation counts. The 80386 in Virtual 8086 Mode does mask rotation counts.

The overflow flag is defined only for the single-rotate forms of the instructions (second operand := 1). It is undefined in all other cases. For left shifts/rotates, the CF bit after the shift is XORed with the high-order result bit. For right shifts/rotates, the high-order two bits of the result are XORed to get OF.

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

REP/REPE/REPZ/REPNE/REPNZ -- Repeat Following String Operation

Operation

 
 
 IF AddressSize = 16
 THEN use CX for CountReg;
 ELSE (* AddressSize = 32 *) use ECX for CountReg;
 FI;
 WHILE CountReg <> 0
 DO
    service pending interrupts (if any);
    perform primitive string instruction;
    CountReg := CountReg - 1;
    IF primitive operation is CMPB, CMPW, SCAB, or SCAW
    THEN
       IF (instruction is REP/REPE/REPZ) AND (ZF=1)
       THEN exit WHILE loop
       ELSE
          IF (instruction is REPNZ or REPNE) AND (ZF=0)
          THEN exit WHILE loop;
          FI;
       FI;
    FI;
 OD;
 

Description

Synonymous forms of REPE and REPNE are REPZ and REPNZ, respectively.

The REP prefixes apply only to one string instruction at a time. To repeat a block of instructions, use the LOOP instruction or another looping construct.

The precise action for each iteration is as follows:

1. If the address-size attribute is 16 bits, use CX for the count register; if the address-size attribute is 32 bits, use ECX for the count register.
2. Check CX. If it is zero, exit the iteration, and move to the next instruction.
3. Acknowledge any pending interrupts.
4. Perform the string operation once.
5. Decrement CX or ECX by one; no flags are modified.
6. Check the zero flag if the string operation is SCAS or CMPS. If the repeat condition does not hold, exit the iteration and move to the next instruction. Exit the iteration if the prefix is REPE and ZF is 0 (the last comparison was not equal), or if the prefix is REPNE and ZF is one (the last comparison was equal).
7. Return to step 1 for the next iteration.

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

Notes

RET -- Return from Procedure

Operation

 
 
 IF instruction = near RET
 THEN;
    IF OperandSize = 16
    THEN
       IP := Pop();
       EIP := EIP AND 0000FFFFH;
    ELSE (* OperandSize = 32 *)
       EIP := Pop();
    FI;
    IF instruction has immediate operand THEN eSP := eSP + imm16; FI;
 FI;
 
 IF (PE = 0 OR (PE = 1 AND VM = 1))
    (* real mode or virtual 8086 mode *)
    AND instruction = far RET
 THEN;
    IF OperandSize = 16
    THEN
       IP := Pop();
       EIP := EIP AND 0000FFFFH;
       CS := Pop(); (* 16-bit pop *)
    ELSE (* OperandSize = 32 *)
       EIP := Pop();
       CS := Pop(); (* 32-bit pop, high-order 16-bits discarded *)
    FI;
    IF instruction has immediate operand THEN eSP := eSP + imm16; FI;
 FI;
 
 IF (PE = 1 AND VM = 0) (* Protected mode, not V86 mode *)
    AND instruction = far RET
 THEN
    IF OperandSize=32
    THEN Third word on stack must be within stack limits else #SS(0);
    ELSE Second word on stack must be within stack limits else #SS(0);
    FI;
    Return selector RPL must be >= CPL ELSE #GP(return selector)
    IF return selector RPL = CPL
    THEN GOTO SAME-LEVEL;
    ELSE GOTO OUTER-PRIVILEGE-LEVEL;
    FI;
 FI;
 
 SAME-LEVEL:
    Return selector must be non-null ELSE #GP(0)
    Selector index must be within its descriptor table limits ELSE
       #GP(selector)
    Descriptor AR byte must indicate code segment ELSE #GP(selector)
    IF non-conforming
    THEN code segment DPL must equal CPL;
    ELSE #GP(selector);
    FI;
    IF conforming
    THEN code segment DPL must be <= CPL;
    ELSE #GP(selector);
    FI;
    Code segment must be present ELSE #NP(selector);
    Top word on stack must be within stack limits ELSE #SS(0);
    IP must be in code segment limit ELSE #GP(0);
    IF OperandSize=32
    THEN
       Load CS:EIP from stack
       Load CS register with descriptor
       Increment eSP by 8 plus the immediate offset if it exists
    ELSE (* OperandSize=16 *)
       Load CS:IP from stack
       Load CS register with descriptor
       Increment eSP by 4 plus the immediate offset if it exists
    FI;
 
 OUTER-PRIVILEGE-LEVEL:
    IF OperandSize=32
    THEN Top (16+immediate) bytes on stack must be within stack limits
       ELSE #SS(0);
    ELSE Top (8+immediate) bytes on stack must be within stack limits ELSE
       #SS(0);
    FI;
    Examine return CS selector and associated descriptor:
       Selector must be non-null ELSE #GP(0);
       Selector index must be within its descriptor table limits ELSE
          #GP(selector)
       Descriptor AR byte must indicate code segment ELSE #GP(selector);
       IF non-conforming
       THEN code segment DPL must equal return selector RPL
       ELSE #GP(selector);
       FI;
       IF conforming
       THEN code segment DPL must be <= return selector RPL;
       ELSE #GP(selector);
       FI;
       Segment must be present ELSE #NP(selector)
    Examine return SS selector and associated descriptor:
       Selector must be non-null ELSE #GP(0);
       Selector index must be within its descriptor table limits
          ELSE #GP(selector);
       Selector RPL must equal the RPL of the return CS selector ELSE
          #GP(selector);
       Descriptor AR byte must indicate a writable data segment ELSE
          #GP(selector);
       Descriptor DPL must equal the RPL of the return CS selector ELSE
          #GP(selector);
       Segment must be present ELSE #NP(selector);
    IP must be in code segment limit ELSE #GP(0);
    Set CPL to the RPL of the return CS selector;
    IF OperandMode=32
    THEN
       Load CS:EIP from stack;
       Set CS RPL to CPL;
       Increment eSP by 8 plus the immediate offset if it exists;
       Load SS:eSP from stack;
    ELSE (* OperandMode=16 *)
       Load CS:IP from stack;
       Set CS RPL to CPL;
       Increment eSP by 4 plus the immediate offset if it exists;
       Load SS:eSP from stack;
    FI;
    Load the CS register with the return CS descriptor;
    Load the SS register with the return SS descriptor;
    For each of ES, FS, GS, and DS
    DO
       IF the current register setting is not valid for the outer level,
          set the register to null (selector := AR := 0);
       To be valid, the register setting must satisfy the following
          properties:
          Selector index must be within descriptor table limits;
          Descriptor AR byte must indicate data or readable code segment;
          IF segment is data or non-conforming code, THEN
             DPL must be >= CPL, or DPL must be >= RPL;
       FI;
    OD;
 

Description

The optional numeric parameter to RET gives the number of stack bytes (OperandMode=16) or words (OperandMode=32) to be released after the return address is popped. These items are typically used as input parameters to the procedure called.

For the intrasegment (near) return, the address on the stack is a segment offset, which is popped into the instruction pointer. The CS register is unchanged. For the intersegment (far) return, the address on the stack is a long pointer. The offset is popped first, followed by the selector.

In real mode, CS and IP are loaded directly. In Protected Mode, an intersegment return causes the processor to check the descriptor addressed by the return selector. The AR byte of the descriptor must indicate a code segment of equal or lesser privilege (or greater or equal numeric value) than the current privilege level. Returns to a lesser privilege level cause the stack to be reloaded from the value saved beyond the parameter block.

The DS, ES, FS, and GS segment registers can be set to 0 by the RET instruction during an interlevel transfer. If these registers refer to segments that cannot be used by the new privilege level, they are set to 0 to prevent unauthorized access from the new privilege level.

Flags Affected

Protected Mode Exceptions

Operation

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

SAHF -- Store AH into Flags

Operation

 
 
 SF:ZF:xx:AF:xx:PF:xx:CF := AH;
 

Description

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

SAL/SAR/SHL/SHR -- Shift Instructions

Operation

 
 
 (* COUNT is the second parameter *)
 (temp) := COUNT;
 WHILE (temp <> 0)
 DO
    IF instruction is SAL or SHL
    THEN CF := high-order bit of r/m;
    FI;
    IF instruction is SAR or SHR
    THEN CF := low-order bit of r/m;
    FI;
    IF instruction = SAL or SHL
    THEN r/m := r/m * 2;
    FI;
    IF instruction = SAR
    THEN r/m := r/m /2 (*Signed divide, rounding toward negative infinity*);
    FI;
    IF instruction = SHR
    THEN r/m := r/m / 2; (* Unsigned divide *);
    FI;
    temp := temp - 1;
 OD;
 (* Determine overflow for the various instructions *)
 IF COUNT = 1
 THEN
    IF instruction is SAL or SHL
    THEN OF := high-order bit of r/m <> (CF);
    FI;
    IF instruction is SAR
    THEN OF := 0;
    FI;
    IF instruction is SHR
    THEN OF := high-order bit of operand;
    FI;
 ELSE OF := undefined;
 FI;
 

Description

SAR and SHR shift the bits of the operand downward. The low-order bit is shifted into the carry flag. The effect is to divide the operand by 2. SAR performs a signed divide with rounding toward negative infinity (not the same as IDIV); the high-order bit remains the same. SHR performs an unsigned divide; the high-order bit is set to 0.

The shift is repeated the number of times indicated by the second operand, which is either an immediate number or the contents of the CL register. To reduce the maximum execution time, the 80386 does not allow shift counts greater than 31. If a shift count greater than 31 is attempted, only the bottom five bits of the shift count are used. (The 8086 uses all eight bits of the shift count.)

The overflow flag is set only if the single-shift forms of the instructions are used. For left shifts, OF is set to 0 if the high bit of the answer is the same as the result of the carry flag (i.e., the top two bits of the original operand were the same); OF is set to 1 if they are different. For SAR, OF is set to 0 for all single shifts. For SHR, OF is set to the high-order bit of the original operand.

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

SBB -- Integer Subtraction with Borrow

Operation

 
 
 IF SRC is a byte and DEST is a word or dword
 THEN DEST := DEST - (SignExtend(SRC) + CF)
 ELSE DEST := DEST - (SRC + CF);
 

Description

When an immediate byte value is subtracted from a word operand, the immediate value is first sign-extended.

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

SCAS/SCASB/SCASW/SCASD -- Compare String Data

Operation

 
 
 IF AddressSize = 16
 THEN use DI for dest-index;
 ELSE (* AddressSize = 32 *) use EDI for dest-index;
 FI;
 IF byte type of instruction
 THEN
    AL - [dest-index]; (* Compare byte in AL and dest *)
    IF DF = 0 THEN IndDec := 1 ELSE IncDec := -1; FI;
 ELSE
    IF OperandSize = 16
    THEN
       AX - [dest-index]; (* compare word in AL and dest *)
       IF DF = 0 THEN IncDec := 2 ELSE IncDec := -2; FI;
    ELSE (* OperandSize = 32 *)
       EAX - [dest-index];(* compare dword in EAX & dest *)
       IF DF = 0 THEN IncDec := 4 ELSE IncDec := -4; FI;
    FI;
 FI;
 dest-index := dest-index + IncDec
 

Description

If the address-size attribute for this instruction is 16 bits, DI is used as the destination register; otherwise, the address-size attribute is 32 bits and EDI is used.

The address of the memory data being compared is determined solely by the contents of the destination register, not by the operand to SCAS. The operand validates ES segment addressability and determines the data type. Load the correct index value into DI or EDI before executing SCAS.

After the comparison is made, the destination register is automatically updated. If the direction flag is 0 (CLD was executed), the destination register is incremented; if the direction flag is 1 (STD was executed), it is decremented. The increments or decrements are by 1 if bytes are compared, by 2 if words are compared, or by 4 if doublewords are compared.

SCASB, SCASW, and SCASD are synonyms for the byte, word and doubleword SCAS instructions that don't require operands. They are simpler to code, but provide no type or segment checking.

SCAS can be preceded by the REPE or REPNE prefix for a block search of CX or ECX bytes or words. Refer to the REP instruction for further details.

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

SETcc -- Byte Set on Condition

Operation

 
 
 IF condition THEN r/m8 := 1 ELSE r/m8 := 0; FI;
 

Description

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

SGDT/SIDT -- Store Global/Interrupt Descriptor Table Register

Operation

 
 
 DEST := 48-bit BASE/LIMIT register contents;
 

Description

SGDT and SIDT are used only in operating system software; they are not used in application programs.

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

Compatability Note

SHLD -- Double Precision Shift Left

Operation

 
 
 (* count is an unsigned integer corresponding to the last operand of the
 instruction, either an immediate byte or the byte in register CL *)
 ShiftAmt := count MOD 32;
 inBits := register; (* Allow overlapped operands *)
 IF ShiftAmt = 0
 THEN no operation
 ELSE
    IF ShiftAmt >= OperandSize
    THEN (* Bad parameters *)
       r/m := UNDEFINED;
       CF, OF, SF, ZF, AF, PF := UNDEFINED;
    ELSE (* Perform the shift *)
       CF := BIT[Base, OperandSize - ShiftAmt];
          (* Last bit shifted out on exit *)
    FOR i := OperandSize - 1 DOWNTO ShiftAmt
    DO
       BIT[Base, i] := BIT[Base, i - ShiftAmt];
    OF;
    FOR i := ShiftAmt - 1 DOWNTO 0
    DO
       BIT[Base, i] := BIT[inBits, i - ShiftAmt + OperandSize];
    OD;
    Set SF, ZF, PF (r/m);
       (* SF, ZF, PF are set according to the value of the result *)
    AF := UNDEFINED;
    FI;
 FI;
 

Description

The count operand is provided by either an immediate byte or the contents of the CL register. These operands are taken MODULO 32 to provide a number between 0 and 31 by which to shift. Because the bits to shift are provided by the specified registers, the operation is useful for multiprecision shifts (64 bits or more). The SF, ZF and PF flags are set according to the value of the result. CS is set to the value of the last bit shifted out. OF and AF are left undefined.

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

SHRD -- Double Precision Shift Right

Operation

 
 
 (* count is an unsigned integer corresponding to the last operand of the
 instruction, either an immediate byte or the byte in register CL *)
 ShiftAmt := count MOD 32;
 inBits := register; (* Allow overlapped operands *)
 IF ShiftAmt = 0
 THEN no operation
 ELSE
    IF ShiftAmt >= OperandSize
    THEN (* Bad parameters *)
       r/m := UNDEFINED;
       CF, OF, SF, ZF, AF, PF := UNDEFINED;
    ELSE (* Perform the shift *)
       CF := BIT[r/m, ShiftAmt - 1]; (* last bit shifted out on exit *)
       FOR i := 0 TO OperandSize - 1 - ShiftAmt
       DO
          BIT[r/m, i] := BIT[r/m, i - ShiftAmt];
       OD;
       FOR i := OperandSize - ShiftAmt TO OperandSize - 1
       DO
          BIT[r/m,i] := BIT[inBits,i+ShiftAmt - OperandSize];
       OD;
       Set SF, ZF, PF (r/m);
          (* SF, ZF, PF are set according to the value of the result *)
       Set SF, ZF, PF (r/m);
       AF := UNDEFINED;
    FI;
 FI;
 

Description

The count operand is provided by either an immediate byte or the contents of the CL register. These operands are taken MODULO 32 to provide a number between 0 and 31 by which to shift. Because the bits to shift are provided by the specified register, the operation is useful for multi-precision shifts (64 bits or more). The SF, ZF and PF flags are set according to the value of the result. CS is set to the value of the last bit shifted out. OF and AF are left undefined.

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

SLDT -- Store Local Descriptor Table Register

Operation

 
 
 r/m16 := LDTR;
 

Description

SLDT is used only in operating system software. It is not used in application programs.

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

Notes

SMSW -- Store Machine Status Word

Operation

 
 
 r/m16 := MSW;
 

Description

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

Notes

STC -- Set Carry Flag

Operation

 
 
 CF := 1;
 

Description

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

STD -- Set Direction Flag

Operation

 
 
 DF := 1;
 

Description

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

STI -- Set Interrupt Flag

Operation

 
 
 IF := 1
 

Description

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

STOS/STOSB/STOSW/STOSD -- Store String Data

Operation

 
 
 IF AddressSize = 16
 THEN use ES:DI for DestReg
 ELSE (* AddressSize = 32 *) use ES:EDI for DestReg;
 FI;
 IF byte type of instruction
 THEN
    (ES:DestReg) := AL;
    IF DF = 0
    THEN DestReg := DestReg + 1;
    ELSE DestReg := DestReg - 1;
    FI;
 ELSE IF OperandSize = 16
    THEN
       (ES:DestReg) := AX;
       IF DF = 0
       THEN DestReg := DestReg + 2;
       ELSE DestReg := DestReg - 2;
       FI;
    ELSE (* OperandSize = 32 *)
       (ES:DestReg) := EAX;
       IF DF = 0
       THEN DestReg := DestReg + 4;
       ELSE DestReg := DestReg - 4;
       FI;
    FI;
 FI;
 

Description

The destination operand must be addressable from the ES register. A segment override is not possible.

The address of the destination is determined by the contents of the destination register, not by the explicit operand of STOS. This operand is used only to validate ES segment addressability and to determine the data type. Load the correct index value into the destination register before executing STOS.

After the transfer is made, DI is automatically updated. If the direction flag is 0 (CLD was executed), DI is incremented; if the direction flag is 1 (STD was executed), DI is decremented. DI is incremented or decremented by 1 if a byte is stored, by 2 if a word is stored, or by 4 if a doubleword is stored.

STOSB, STOSW, and STOSD are synonyms for the byte, word, and doubleword STOS instructions, that do not require an operand. They are simpler to use, but provide no type or segment checking.

STOS can be preceded by the REP prefix for a block fill of CX or ECX bytes, words, or doublewords. Refer to the REP instruction for further details.

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

STR -- Store Task Register

Operation

 
 
 r/m := task register;
 

Description

STR is used only in operating system software. It is not used in application programs.

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

Notes

SUB -- Integer Subtraction

Operation

 
 
 IF SRC is a byte and DEST is a word or dword
 THEN DEST := DEST - SignExtend(SRC);
 ELSE DEST := DEST - SRC;
 FI;
 

Description

When an immediate byte value is subtracted from a word operand, the immediate value is first sign-extended to the size of the destination operand.

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

TEST -- Logical Compare

Operation

 
 
 DEST := LeftSRC AND RightSRC;
 CF := 0;
 OF := 0;
 

Description

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

VERR, VERW -- Verify a Segment for Reading or Writing

Operation

 
 
 IF segment with selector at (r/m) is accessible
    with current protection level
    AND ((segment is readable for VERR) OR
       (segment is writable for VERW))
 THEN ZF := 0;
 ELSE ZF := 1;
 FI;
 

Description

• The selector must denote a descriptor within the bounds of the table (GDT or LDT); the selector must be "defined."
• The selector must denote the descriptor of a code or data segment (not that of a task state segment, LDT, or a gate).
• For VERR, the segment must be readable. For VERW, the segment must be a writable data segment.
• If the code segment is readable and conforming, the descriptor privilege level (DPL) can be any value for VERR. Otherwise, the DPL must be greater than or equal to (have less or the same privilege as) both the current privilege level and the selector's RPL.

Flags Affected

Protected Mode Exceptions

#GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page fault

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

WAIT -- Wait until BUSY# Pin is Inactive (HIGH)

Description

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

XCHG -- Exchange Register/Memory with Register

Operation

 
 
 temp := DEST
 DEST := SRC
 SRC := temp
 

Description

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

XLAT/XLATB -- Table Look-up Translation

 
 
 D7    XLAT m8    5     Set AL to memory byte DS:[(E)BX + unsigned AL]
 D7    XLATB      5     Set AL to memory byte DS:[(E)BX + unsigned AL]
 

Operation

 
 
 IF AddressSize = 16
 THEN
    AL := (BX + ZeroExtend(AL))
 ELSE (* AddressSize = 32 *)
    AL := (EBX + ZeroExtend(AL));
 FI;
 

Description

The operand to XLAT allows for the possibility of a segment override. XLAT uses the contents of BX even if they differ from the offset of the operand. The offset of the operand should have been moved intoBX/EBX with a previous instruction.

The no-operand form, XLATB, can be used if the BX/EBX table will always reside in the DS segment.

Flags Affected

Protected Mode Exceptions

Real Address Mode Exceptions

Virtual 8086 Mode Exceptions

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